It is common in circuit designs to have different microchips interconnected via digital interface. The digital interface can cause noise in a circuit. For example, fast transitions or signal edges on a signal transmitted between two microchips over a printed circuit board (PCB) trace between the microchips cause disturbances that may result in crosstalk or electromagnetic interference. The push toward higher-speed circuits increases the exposure to crosstalk and interference problems, seeing that shorter transition times result in greater crosstalk and interference. In addition, short rise times place an extra burden on the PCB layout, as impedance irregularities or stubs are more likely to cause reflections that harm signal integrity. Thus, when designing a digital interface between two microchips, it is often advantageous to have control over the signal transition times on the interface line. Some interface designs have a variable transition time, or slew rate, which allows a designer to use the slowest possible edge speed that satisfies the timing goals of the digital interface.
In addition to the crosstalk and interference discussed above, fast transitions require more transient current from the power supply. The transient current used by a digital driver circuit can be a significant factor in the performance of the interfacing microchips. The inductance of the power supply bond wires and leads combines with the inherent on-chip supply capacitance to create a resonant circuit. Fast rise time in transient supply current, or sharp transient current, can excite the resonant circuit causing ringing on the supply voltages. Such ringing in turn couples into the substrate of the microchip, which can interfere with circuitry throughout the chip. Digital line drivers often have the sharpest current transients of any circuit on a microchip, often with the highest magnitude transient, meaning the digital line driver may be responsible for significant overall microchip noise.
Transient currents with large peak amplitudes (large di/dt) may also cause problems with power supply droop, which results when the current travels through the finite resistance of the supply wires/traces throughout the microchip. As a result, supply voltage at various locations along the supply wires/traces may be lower than at the source. Observe that the power supply will also have an inherent inductance, L, which will result in an increased voltage drop with large di/dt, due to the known relationship with voltage and Ldi/dt.
Most common digital drivers are similar or the same layout as a CMOS (complimentary metal-oxide-semiconductor) inverter. A large PMOS (positively-doped metal-oxide-semiconductor, or p-type) transistor pulls up the line voltage during a rising edge, and a large NMOS (negatively-doped metal-oxide-semiconductor, or n-type) transistor pulls down the line voltage during a falling edge. The advantages to such a digital driver is that it is simple, small (very efficient in use of die area), and can handle high switching speeds. However, there are several disadvantages to the inverter design. Although the circuit is generally fast, the edge speed is very sensitive to variations in temperature, power supply voltage, and manufacturing parameters. Transition times may exhibit a four to one or even five to one variation. Thus, the inverter design results in timing uncertainty and potentially very high di/dt and peak currents.
One known approach to reducing di/dt in the power supply is with a series of output transistors, rather than a simple inverter design. Such an approach is illustrated by circuit 100 of FIG. 1. FIG. 1 is a representation of a prior art digital delay line driver. Circuit 100 has a more gradual turn on of the output than the simple inverter design. Input IN 106 is passed to the gates of each of the series transistors. P112, P114, P116, and P118 are PMOS transistors to pull up output line OUT108 on a rising edge to voltage source V102, and N122, N124, N126, and N128 are NMOS transistors to pull down OUT108 on a falling edge to ground/reference G104. Resistors R132, R134, R136, and R138 are in the gates of transistors P112, P114, P116, and P118, respectively, while resistors R142, R144, R146, and R148 are in the gates of transistors N122, N124, N126, and N128, respectively. The resistors before each gate combine with the capacitance of the gate to form an RC delay line. The voltage drop across each successive series resistor causes a delay in the gate voltage of each successive transistor from reaching an active state. Thus, each gate turns on one at a time, resulting in an overall output current that is much more gradual than turning on the transistors all at the same time (essentially eliminating the resistors in the gates of the transistors). The slew rate of circuit 100 is slower than the simple inverter design. Note that for purposes of simplicity in description, each of the digital line drivers shown in the Figures is illustrated with four transistors. The teachings herein could be applied equally well to a digital delay line driver having multiple transistors of a number more or fewer than four.
One significant disadvantage of circuit 100 is that the turn off of the transistors will occur in a staggered fashion, just as the turn on is staggered. The staggering of the turn off of the transistors results in “crowbar” or “shoot through” current (referred to herein as crowbar current). Crowbar current occurs during the transition of the output signal, for example, when the first pull down transistors (e.g., N122) is conducting prior to the turn off of the last pull up transistors (e.g., P118). The reverse also results in crowbar current, for example, when P112 turns on prior to the turn off of N128. When both pull up and pull down transistors are simultaneously conducting, there is a low impedance path created between power and ground, allowing large currents to flow from power to ground. Simultaneous conduction of the pull up and pull down circuit elements not only wastes power, but also causes a large supply droop and ground bounce.
Thus, there are significant performance disadvantages to both the simple inverter design digital line driver, as well as a conventional digital delay line driver. The disadvantages discussed above result in power inefficiency and noise in the microchip. The disadvantages are increasingly significant in higher-speed microchips.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.